In deeply pipelined processors, successful dynamic branch prediction is crucial to high speed operation. Consequently, a number of branch prediction mechanisms have been developed. One specific mechanism is the Gshare branch prediction mechanism in which a vector is created which captures the outcome of a fixed number of branches that have been fetched immediately before the current instruction fetch. This vector is typically created by shifting a logic 1 or logic 0 into the last position of a shift register when the outcome of a given branch is determined, with a logic 1 representing a branch taken outcome and a logic 0 representing a branch not taken outcome. The bits of the vector are then bitwise XORed with appropriate bits of the current address. The resulting address is used to index into a branch history table entry which typically is a counter which maintains a value which is used for making the prediction (taken/not taken) for the branch.
In highly pipelined superscalar processors, however, instructions are fetched into the pipeline well in advance of their actual execution. As a result, in a high frequency processor, the vector in a conventional Gshare register will be based on branch outcomes which have been determined several cycles before the predicted execution of the current instruction. In other words, outcome data for more temporally proximate branches are not available in the vector at the time the vector is needed to make the current prediction.
Consequently, the need has arisen for circuits and methods for improving branch prediction accuracy. Such circuits and methods should not unnecessarily complicate the existing instruction pipeline structure and should not substantially impact the instruction pipeline timing.